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cleaved wafers can be accepted as long as it does not cause a significant drop in the sensitivity (from a quarter to a half of a wafer)
If wafer and stage cleanness is maintained
1-0217 (Reapproved 0423)
World Fab Watch
By describing a generic process flow
MF172700 - SEMI MF1727 - Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers Revision:SEMI MF1727-1110 (Reapproved 0322) - Current cleaved wafers can be acceptedNOTICE: This Document was reapproved with minor editorial changes. Defects induced by thermal processing of silicon wafers may adversely influence device performance and yield. These defects are influenced directly by contamination, ambient atmosphere, temperature, time at temperature, and rate of change of temperature to which the specimens are subjected. Conditions vary significantly among device manufacturing technologies. The thermal cycling
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