PV04000 - SEMI PV40 - Test Method for In-Line Measurement of Saw Marks on PV Silicon Wafers by a Light Sectioning Technique Using Multiple Line Segments StdTpc-Silicon 3 Background

3  Background

SEMI E82-0703 (technical revision)

which do not depend on surface passivation

down to the detail of each fab

Both constant-current and constant-voltage TDDB methods can be used as an evaluation of gate oxide lifetime

PV04000 - SEMI PV40 - Test Method for In-Line Measurement of Saw Marks on PV Silicon Wafers by a Light Sectioning Technique Using Multiple Line Segments StdTpc-Silicon 3 BackgroundSilicon (Si) wafers for PV applications cut from a Si ingot or Si brick contain a variety of micro and macroscopic crystallographic defects and flaws that may impact the efficiency of a solar cells or the yield of a manufacturing line. Theses defects can be categorized by their origin, either as grown in defects that are generated during the solidification of the Si ingot or as process induced defects that are generated by abrasive processes during